The use of pipelining in a processor to improve efficiency

1.1.1 Structure and function of the processor

Structure and function of the processor — Note 4 of 5

Candidates need to understand what is meant by pipelining and how it allows the fetch, decode and execute stages of different instructions to overlap. Candidates need to understand how pipelining improves processor efficiency, and why branch instructions can cause the pipeline to be flushed.

What you need to know

Pipelining allows the processor to work on several instructions at once by overlapping the stages of the fetch-decode-execute cycle. While one instruction is being executed, the next can be decoded and the one after that fetched, so the processor completes more instructions in the same time.

What to know

With a full pipeline, one instruction can COMPLETE every cycle, even though each instruction still takes three cycles from start to finish.
Data dependencies can also stall the pipeline, for example when an instruction needs the result of the instruction just before it.

Key terms

Exam tipCommon mistake

Pipelining: Overlapping the fetch, decode and execute stages so that different instructions are at different stages at the same time.
Without pipelining, a three-stage instruction takes three cycles and the next instruction cannot start until it finishes.
Pipelining improves throughput (instructions completed per second), not the time taken for a single instruction.
RISC processors suit pipelining well because their instructions are simple and take a similar time, so each stage is balanced.
Common mistake: Saying pipelining makes each instruction run faster. Each instruction takes the same time; more instructions are in progress at once.
Pipeline flush: When a branch (jump) instruction is executed, the instructions already fetched and decoded behind it are no longer needed and must be discarded, so the pipeline has to refill.

Exam technique

Tip:Be ready to complete a pipeline table showing which instruction is at which stage in each clock cycle.

Code examples

Three-stage pipeline: one instruction completes each cycle once the pipeline is full

text

Cycle:     1      2      3      4      5
Fetch:     I1     I2     I3     I4     I5
Decode:           I1     I2     I3     I4
Execute:                 I1     I2     I3

If I2 is a branch, I3 and I4 (already fetched/decoded)
are discarded and the pipeline is flushed.