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Knowledge/A Level/H446/01 Computer systems/Structure and function of the processor/The ALU, Control Unit, registers…

The ALU, Control Unit, registers (PC, ACC, MAR, MDR, CIR) and buses

The Arithmetic and Logic Unit; ALU, Control Unit Registers: Program Counter; PC, Accumulator; ACC, Memory Address Register; MAR, Memory Data Register; MDR, Current Instruction Register; CIR Buses: data, address and control: how this relates to assembly language programs

1.1.1 Structure and function of the processor

Practise exam questions

Structure and function of the processor — Note 1 of 5

Candidates need to have an understanding of the purpose and function of the core components of a processor. Candidates need to understand the role and components of the ALU. Candidates need to understand the purpose and function or registers within the processor, including the PC, accumulator, MAR, MDR and CIR. Candidates need to understand the purpose, function and role of the data, address and control buses in the processor. Candidates need to understand how assembly language makes use of registers, and how data and addressed are transferred between registers.

What you need to know

The processor is made up of the Arithmetic Logic Unit (ALU), the Control Unit (CU) and a set of registers, connected to main memory by three buses. At A Level you need to know the purpose of each register and bus, and how they are used when an assembly language instruction is carried out.

What to know

  • Link to assembly language: an instruction such as LDA 20 puts address 20 in the MAR, the value at address 20 arrives in the MDR via the data bus, and is then copied into the accumulator.

Key terms

Exam tipCommon mistake

ALUArithmetic Logic Unit

Carries out arithmetic operations (addition, subtraction, shifts) and logical operations (AND, OR, NOT, comparisons). Results are usually stored in the accumulator.

CUControl Unit

Decodes instructions and sends control signals to coordinate the movement of data around the processor and to memory and I/O devices.

Register

A very small, very fast storage location inside the processor that holds data, an address or an instruction during processing.

PCProgram Counter

Holds the ADDRESS of the next instruction to be fetched.

ACCAccumulator

Holds the data currently being processed and the RESULTS of operations carried out by the ALU.

MARMemory Address Register

Holds the ADDRESS of the memory location about to be read from or written to.

MDRMemory Data Register

Holds the DATA or instruction that has just been read from memory, or is about to be written to memory.

CIRCurrent Instruction Register

Holds the instruction currently being decoded and executed, split into an opcode and an operand.

Data bus

Carries data and instructions between the processor, memory and I/O. It is BIDIRECTIONAL. Its width (number of lines) determines how many bits can be transferred at once.

Address bus

Carries memory addresses FROM the processor to memory. It is UNIDIRECTIONAL. Its width determines how many locations can be addressed: n lines = 2^n addresses.

  • Common mistake: Saying the address bus is bidirectional. Addresses only ever travel from the processor to memory.
Control bus

Carries control signals such as memory read, memory write, clock, interrupt request and bus request. It is BIDIRECTIONAL.

Exam technique

  • Tip:Be precise about what a register HOLDS: the PC and MAR hold ADDRESSES; the MDR and ACC hold DATA; the CIR holds an INSTRUCTION.
  • Example:'Explain the effect of increasing the width of the address bus.' More address lines means more memory locations can be addressed (each extra line doubles it), so more memory can be used.

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Practise 1.1.1 questions
Next note →The Fetch-Decode-Execute cycle and its effects on registers1.1.1 Structure and function of the processor

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Structure and function of the processor

Note 1 of 5

  1. 1The ALU, Control Unit, registers (PC, ACC, MAR, MDR, CIR) and buses
  2. 2The Fetch-Decode-Execute cycle and its effects on registers
  3. 3Factors affecting CPU performance: clock speed, number of cores, cache
  4. 4The use of pipelining in a processor to improve efficiency
  5. 5Von Neumann, Harvard and contemporary processor architecture
Topic overview